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NCL30051
PFC Startup
The output of the error amplifier is pulled low with an
internal pull down transistor when the supply voltage has
not reached V CC(on) or if there is a PFC undervoltage fault.
This ensures a soft ? start sequence once the PFC is enabled
Drain
Voltage of
PFC Switch
PDRV
and eliminates output voltage overshoot during on/off
tests. Once the error amplifier is enabled the output of the
error amplifier charges quickly to the minimum clamp
voltage.
V PZCD
10 V
V ZCD(high)
V ZCD(low)
0V
RPZCD
Off Time Control
The PFC off time varies with the instantaneous line
voltage and it is adjusted every cycle to allow the inductor
current to reach zero before the next switch cycle begins.
The inductor is demagnetized once its current reaches zero.
Once the inductor is demagnetized the drain voltage of the
PFC switch begins to drop. The inductor demagnetization
is detected by sensing the voltage across the inductor using
an auxiliary winding. This winding is commonly known as
a zero crossing detector (ZCD) winding. This winding
provides a scaled version of the inductor voltage. Figure 6
shows the ZCD winding arrangement.
+ +
Rectified
ac line PFC
voltage M1 Output
? PFC Voltage
Drive
Signal ?
PZCD
Figure 6. ZCD Winding Implementation
A negative voltage appears on the ZCD winding while
the PFC switch is on. The PZCD voltage is positive while
Figure 7. ZCD Winding Waveforms
During startup there are no ZCD transitions to enable the
PFC switch. A watchdog timer enables the PFC controller
if no switch pulses are detected for a period of 180 m s
(typical). The watchdog timer is also useful while
operating at light load because the amplitude of the ZCD
signal may be very small to cross the ZCD thresholds. The
watchdog timer is reset at the beginning of a PFC drive
pulse and in a PFC undervoltage fault.
The watchdog timer is disabled if the voltage on the
PZCD pin is above V ZCD(high) . It is re ? enabled once the
voltage on the PZCD pin drops below V ZCD(low) . Disabling
the watchdog timer allows the PFC to be disabled by
pulling up on the PZCD pin. Care should be taken to limit
the current into the PZCD pin to prevent exceeding the
internal 10 V zener clamp.
PFC Compensation
A transconductance error amplifier regulates the PFC
output voltage, Vbulk, by comparing the PFC feedback
signal to an internal 2.5 V reference. As shown in Figure 8
a resistor divider from the PFC output voltage consisting of
R1 and R2 generates the PFC feedback signal.
Vbulk
the PFC switch is off and current is flowing through the
inductor. The PZCD voltage drops to and rings around zero
volts once the inductor is demagnetized. Once a negative
transition is detected in the PZCD pin the next switch cycle
commences. A positive transition (corresponding to the
R1
R2
PFB
I PFB ?
PFC Error
Amplifier
+
V PREF
PFC switch turn off) arms the ZCD detector to prevent false
triggering. The arming of the ZCD detector is typically
2.1 V (V PZCD increasing) and the triggering is typically
1.5 V (V PZCD decreasing).
The PZCD pin is internally clamped to 10 V with a zener
diode. A resistor in series with the ZCD pin is required to
limit the current into the PZCD pin. The zener diode
prevents the voltage from exceeding the 10 V clamp or
going below ground. Figure 7 shows typical ZCD
waveforms.
Figure 8. PFC Voltage Sensing
The feedback signal is applied to the amplifier inverting
input. The internal 2.5 V reference, V PREF , is applied to the
amplifier non ? inverting input. The reference is trimmed
during manufacturing to achieve an accuracy of ± 3.2%.
Figure 8 shows the PFC error amplifier and sensing
network. Equation 5 is used to calculate the values of the
PFC feedback network.
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